This invention relates to a semiconductor device such as DRAM, SRAM, EEPROM, mask ROM, in which cells are formed in an integrated circuit region, and particularly relates to a countermeasure for preventing insulation defect in a dummy cell provided around the integrated circuit region.
Conventionally, a semiconductor device having a memory function such as a DRAM is generally composed of a memory cell part in which a plurality of cells for memorizing information is arranged and a peripheral circuit part for controlling read-out, write-in and erasure of information. The peripheral circuit part has comparatively low pattern density and the memory cell part has high pattern density. The resolution of stepper is liable to be sensitive to change of the pattern density. Thus, the pattern of the memory cell part at the boundary to the peripheral circuit part is fractured when the pattern density of the memory cell part becomes so high to reach to resolution limit of the stepper, in the recent time.
In order to prevent the disadvantages due to pattern fracture, a well known technique is proposed such as in Laid Open unexamined Japanese Patent Application No. 61-214559 that a semiconductor comprises a peripheral circuit part and a memory cell part in which unit cells are located in the form of matrix, wherein each cell located at an outer peripheral part of the memory cell part serves as a dummy cell. In other words, the dummy cell has a semiconductor element having almost the same construction as a unit cell within a normal memory cell, namely the same construction as a field effect transistor, while not functioning as a memory.
However, the above conventional semiconductor device has following problems since the dummy cell provided at the outer peripheral part of the memory cell part has the element with the same construction as the field effect transistor, while not functioning as the memory.
FIG. 7 shows the state in case where the dummy cell has the same construction as that of a unit cell of the memory cell part. In the figure, reference numeral 50 denotes the memory cell part. 60 denotes a dummy cell part. 51 denotes a unit cell provided at the memory cell part 50 and can function as a memory. The unit cell 51 is composed of a gate 52, a source/drain region 53, a bit-line contact 55 connecting to the source/drain region 53, a storage node formed above the source/drain region 53, and a storage node contact 57 connecting to the source/drain region 53. Reference numeral 61 denotes a dummy cell located in the dummy cell part 60 and it is provided with the gate 52, the source region 65, the storage node 56 and the storage node contact 57.
In the dummy cell part 60, the pattern fracture is often caused by degradation of resolution of the stepper. Short between the dummy cells 61 as shown by an array in broken line in FIG. 7 (including short between the storage nodes 56) and punch-through shown by a dotted line due to fracture of polysilicon pattern may be caused by pattern disturbance in the dummy cell part 60, so that short between the unit cells 51 through the dummy cell as shown by an array in solid line in FIG. 7 is caused.
The present invention has its object of improving reliability of a semiconductor device by providing means for effectively preventing insulation defect described above in a semiconductor integrated circuit having a dummy cell part.